A computer system generally includes one or more processors, a memory and an input/output system. The memory stores data and instructions for processing the data. The processor(s) process the data in accordance with the instructions, and store the processed data in the memory. The input/output system facilitates loading of data and instructions into the system, and obtaining processed data from the system.
Modern memories provide a number of individually addressable storage locations in dynamic random access memories (DRAMs), with each addressable location comprising, for example, eight "bit" (for "binary digit") storage locations. The DRAMs are formed from a plurality of integrated circuit memory chips, with each memory chip storing one or several bits of a number of the eight-bit storage locations. Typically, storage locations on a DRAM chip are arranged in a storage array having a plurality of rows and columns. When a storage location is accessed, that is, when data is written thereto or read therefrom, an address is provided which is divided into a row address portion and a column address portion. Generally, signals representing the row address portion are coupled to address terminals on the memory chips along with a row address strobe ("RAS") signal which enables the chips to use the signals to identify the row of the storage array containing the bit storage locations to be accessed. A selected time thereafter, signals representing the column address portion are coupled to the address terminals, along with a column address strobe ("CAS") signal that enables the chips to use the signals to identify the column. The bit storage locations at the intersection of the identified row and column are written or read, depending on the condition of a write enable signal.
Each bit storage location of a DRAM is essentially a transistor having a large internal capacitance, with the presence of an electrical charge in the capacitance indicating, for example, the binary value "one," and the absence of a charge indicating the binary value "zero." Typically, when a storage location is read, the charge condition of the capacitance is destroyed, and the circuitry in the DRAM chip includes circuitry that restores the charge to its level prior to the read operation. Over time even in the absence of reading operations, the charge levels of the capacitances may decrease due to leakage. The charge levels must be restored, that is "refreshed," to maintain the integrity of the charge, and, accordingly, of the value, representing the data stored in the bit storage location. Therefore, memories which incorporate DRAM chips have refresh circuitry which enables the chips to be refreshed.
In the past, DRAM chips were refreshed by supplying address signals identifying a row of the storage array, along with the RAS signal. This essentially enabled the DRAM chips to read the entire row identified by the row address which enabled their refresh circuitry to refresh the entire row. Control circuitry, external to the DRAM chips, maintained a "refresh counter" which supplied the row address signals, and incremented between refresh operations to ensure that the rows were iteratively refreshed. The time between refreshes was established to ensure that all of the rows would be refreshed before leakage obliterated the data stored therein.
More recently, the DRAM chips have been developed which include the refresh counters. For those chips, refresh is enabled, by external control circuitry, by providing the RAS signal and the CAS signal in reverse order, that is, by providing the CAS signal a selected time before the RAS signal. The DRAM chips, upon receiving the CAS and RAS signals in that manner, refresh the particular rows identified by their respective refresh counters.